Survey of Posit Hardware and Software Development Efforts (July 2019)


Please contact the
NGA team for any updates with regards to the below table.

 

Legend:

 

Hardware

 

Software

 

Hardware & Software

 

Recently Updated

 

Project

Type

Precisions

Quire
Support?

Speed

Testing

Notes

A*STAR

SoftPosit

(Cerlane Leong)

 

Endorsed by NGA Team

C library based on Berkeley SoftFloat

 

C++ wrapper to override operators

 

Python wrapper using SWIG of SoftPosit

8, 16, 32 published and complete;

 

Yes

~60 to 110 Mpops/s on x86 core (Broadwell)

8: Exhaustive;

16: Exhaustive except FMA, quire

32: Exhaustive test is still in progress.

No known bugs.

Fastest and most comprehensive C library for posits presently. Open source license. Designed for plug-in comparison of IEEE floats and posits.

A*STAR “posit4.nb” (John Gustafson)

 

Endorsed by NGA Team

Mathematica notebook

All

Yes

< 80 kpops/s

Exhaustive for low precisions. No known bugs.

Original definition and prototype. Most complete environment for comparing IEEE floats and posits. Open source (MIT license). Many examples of use, including linear solvers

A*STAR “posithub.org” (Cerlane Leong)

Endorsed by NGA Team

JavaScript widget

Convert decimal to posit 6, 8, 16, 32; generate tables 2–17 with es 1–4.

NA

NA; interactive widget

Fully tested

Table generator and conversion

Stillwater Supercomputing, Inc

(Theo Omtzigt)

C++ template library

 

C library

 

Python wrapper

 

Golang library

Arbitrary precision posit float valid (p)

Unum type 1 (p)

Unum type 2 (p)

Arbitrary quire configurations with programmable capacity

posit<4,0> 1GPOPS

posit<8,0> 130MPOPS

posit<16,1> 115MPOPS

posit<32,2> 105MPOPS

posit<64,3>

50MPOPS

posit<128,4>

1MPOPS

posit<256,5>

800KPOPS

 

Complete validation suite for arbitrary posits

 

Randoms for large posit configs.

 

Uses induction to prove nbits+1 is correct

 

no known bugs

 

Open source. MIT license 

 

fully integrated with C/C++ types and automatic conversions

 

Supports full C++ math library (native and conversion to/from IEEE)

 

Runtime integrations: MTL4/MTL5, Eigen, Trilinos, HPR-BLAS

 

Application integrations:

G+SMO, FDBB, FEniCS, ODEintV2, TVM.ai 

 

Hardware Accelerator integration (Xilinx, Intel, Achronix)

Speedgo (Chung Shin Yee)

Python library

All

No

~20 Mpops/s

Extensive; no known bugs

Open source (MIT license)

Softposit Bindings for Racket (David Thien)

Racket

Based on softposit

Yes

Unknown

Unknown

 

Softfloat and softposit in Python (Bill Zorn)

Python library

Based on softposit

Yes

~20-45 Mpops/s on 4.9 GHz Skylake core

Unknown

 

Octave Implementation (Diego Coelho)

Octave Implementation

All

No

Unknown

Limited Testing; no known bugs

GNU General Public License

“Sigmoid Numbers”(Isaac Yonemoto)

Julia library

All <32, all ES

Yes

Unknown

No known bugs (posits).

Division bugs (valids)

Leverages Julia’s templated mathematics standard library, can natively do matrix and tensor operations, complex numbers, FFT, DiffEQ. Support for valids

FastSigmoid” (Isaac Yonemoto)

Julia and C/C++ library

8, 16, 32, all ES

No

Unknown

Known bug in 32-bit multiplication

Used by LLNL in shock studies

SoftPosit for Julia (Milan Klöwer)

Julia library

Based on softposit;

8-bit (es=0..2)

 

16-bit (es=0..2)

 

24-bit (es=1..2)

 

32-bit
(es=2)

Yes

Similar to

A*STAR

SoftPosit

(Cerlane Leong)

Yes:
Posit (8,0),
Posit (16,1),
Posit (32,2)

Other formats lack full functionality 

Supports basic linear algebra functions in Julia (Matrix multiplication, Matrix solve, Elgen decomposition, etc)

 

Open source. Issues and suggestions on github.

This project was developed due to the fact that SigmoidNumbers and FastSigmoid by Isaac Yonemoto is not maintained currently.

PySigmoid” Ken Mercado

Python library

All

Yes

< 20 Mpops/s

Unknown

Open source (MIT license). Easy-to-use interface. Neural net example. Comprehensive functions support.

Jorge Aparicio

Rust library

8 (es = 1)

No

Unknown

Unknown, but probably exhaustive

Very small subset of posit environment

Emanuele Ruffaldi

C++ library

4 to 64 (any es value); “Template version is 2 to 63 bits”

No

Unknown

A few basic tests

4 levels of operations working with posits. Special support for NaN types (nonstandard)

bfp (Beyond Floating Point)” Clément Guérin

C++ library

Any

No

Unknown

Bugs found; status of fixes unknown

Supports + – × ÷   reciprocal, negate, compare

Untitled Verilog Effort (Isaac Yonemoto)

Julia and Verilog

8, 16, 32, ES=0

No

Unknown

Comprehensively tested for 8-bit, no known bugs

Intended for Deep Learning applications Addition, Subtraction and Multiplication only. A proof of concept matrix multiplier has been built, but is off-spec in its precision

Lombiq Technologies

(Zoltán Lehóczky and team)

C# with Hastlayer for hardware generation

8, 16, 32.
(64bits in progress)

Yes

10 Mpops/s

Click here for more

Partial

Requires Microsoft .Net APIs

Deepfloat
(Jeff Johnson, Facebook)

SystemVerilog

Any (parameterized SystemVerilog)

Yes

N/A
(RTL for FPGA/ASIC designs)

Limited

Doesn’t strictly conform to posit spec.

Supports +,-,/,*. Implements both logarithmic posit and normal, “linear” posits

 

License: CC-BY-NC 4.0 at present

Tokyo Tech (Artur Podobas)

FPGA

16, 32, extendable

No

“2 GHz”, not translated to Mpops/s

Partial; known rounding bugs

Yet to be open-source

PACoGen: Posit Arthmetic Core Generator

(Manish Kumar Jaiswal)

Verilog HDL for Posit Arithmetic

Any Precision.

Able to generate any combination of word-size (N) and exponent-size (ES)

No

Speed of design is based on the underlying hardware platform (ASIC/FPGA)

Exhaustive tests for 8-bit posi.
Multi-million random tests are performed for up to 32-bit posit with various ES combinations

It supports rounding-to-nearest rounding method.

Vinay Saxena, Research and Technology Centre, Robert Bosch, India (RTC-IN) and Farhad Merchant, RWTH Aachen University

Verilog generator for VLSI, FPGA

All

No

Similar to floats of same bit size

exhaustive testing (against softposit) for:

- ES=0 | N=8

- ES=2 | N=7,8,9,10,11,12

Selective (20000*65536) combinations for

- ES=1 | N=16  

To be used in commercial products. To the best of our knowledge.

***First ever integration of posits in RISC-V***

Posit Enabled RISC-V Core
(Sugandha Tiwari, Neel Gala, Chester Rebeiro, V.Kamakoti, IIT MADRAS)

BSV (Bluespec System Verilog) Implementation

32-bit posit with (es=2) and (es=3)

No

N/A

Verified against SoftPosit for (es=2) and tested with several applications for (es=2) and (es=3). No known bugs.

First complete posit capable RISC-V core. Supports dynamic switching between (es=2) and (es=3).
More info here.

REX Computing

(Thomas Sohmers)

FPGA version of the “Neo” VLIW processor with posit numeric unit

32

No

~1.2 Gpops/s

Extensive; no known bugs

No divide or square root. First full processor design to replace floats with posits.

Calligo Tech “Posit Numeric Unit (PNU)”

(Vijay Holimath)

FPGA; first working posit hardware

32

Claimed, not yet tested

~0.5 Mpops/s

Extensive tests, not exhaustive. No known bugs.

Single-op accelerator approach; allows direct execution of C codes written for floats. + – × tested; ÷ √ claimed

IBM-TACC (Jianyu Chen)

Specific-purpose FPGA

32

Yes

16–64 Gpops/s

Only one known case tested

Does 128-by-128 matrix-matrix multiplication (SGEMM) using quire.

Manish Kumar Jaiswal

HDL posit generator

Unknown

No

NA

Unknown

Incorrect (truncated) rounding for now; plans to correct