Survey of Posit Hardware and Software Development Efforts (August 2018)


Please contact the
NGA team for any updates with regards to the below table.

 

Project

Type

Precisions

Quire
Support?

Speed

Testing

Notes

A*STAR

SoftPosit

(Cerlane Leong)

 

Endorsed by NGA Team

C library based on Berkeley SoftFloat

 

C++ wrapper to override operators

 

Python wrapper using SWIG of SoftPosit

8, 16, 32 published and complete;

 

Yes

~60 to 110 Mpops/s on x86 core (Broadwell)

8: Exhaustive;

16: Exhaustive except FMA, quire

32: Exhaustive test is still in progress.

No known bugs.

Fastest and most comprehensive C library for posits presently. Open source license. Designed for plug-in comparison of IEEE floats and posits.

A*STAR “posit4.nb” (John Gustafson)

 

Endorsed by NGA Team

Mathematica notebook

All

Yes

< 80 kpops/s

Exhaustive for low precisions. No known bugs.

Original definition and prototype. Most complete environment for comparing IEEE floats and posits. Open source (MIT license). Many examples of use, including linear solvers

A*STAR “posithub.org” (Cerlane Leong)

Endorsed by NGA Team

JavaScript widget

Convert decimal to posit 6, 8, 16, 32; generate tables 2–17 with es 1–4.

NA

NA; interactive widget

Fully tested

Table generator and conversion

Posit Research / Stillwater Technologies

(Theo Omtzigt)

C++ template library

All

Yes

~2 Mpops/s

(for small posits (<=8?), fast lookup table version exists)

Exhaustive tests for range <3,0> to <12,3>.

Extensive testing for other ranges. Some bugs in the “correct answer” source

Open source. Ports in progress to TensorFlow, linear algebra libraries, other applications

Speedgo (Chung Shin Yee)

Python library

All

No

~20 Mpops/s

Extensive; no known bugs

Open source (MIT license)

Softposit Bindings for Racket (David Thien)

Racket

Based on softposit

Yes

Unknown

Unknown

 

Softfloat and softposit in Python (Bill Zorn)

Python library

Based on softposit

Yes

~20-45 Mpops/s on 4.9 GHz Skylake core

Unknown

 

Octave Implementation (Diego Coelho)

Octave Implementation

All

No

Unknown

Limited Testing; no known bugs

GNU General Public License

“Sigmoid Numbers”(Isaac Yonemoto)

Julia library

All <32, all ES

Yes

Unknown

No known bugs (posits).

Division bugs (valids)

Leverages Julia’s templated mathematics standard library, can natively do matrix and tensor operations, complex numbers, FFT, DiffEQ. Support for valids

FastSigmoid” (Isaac Yonemoto)

Julia and C/C++ library

8, 16, 32, all ES

No

Unknown

Known bug in 32-bit multiplication

Used by LLNL in shock studies

PySigmoid” Ken Mercado

Python library

All

Yes

< 20 Mpops/s

Unknown

Open source (MIT license). Easy-to-use interface. Neural net example. Comprehensive functions support.

Jorge Aparicio

Rust library

8 (es = 1)

No

Unknown

Unknown, but probably exhaustive

Very small subset of posit environment

Emanuele Ruffaldi

C++ library

4 to 64 (any es value); “Template version is 2 to 63 bits”

No

Unknown

A few basic tests

4 levels of operations working with posits. Special support for NaN types (nonstandard)

bfp (Beyond Floating Point)” Clément Guérin

C++ library

Any

No

Unknown

Bugs found; status of fixes unknown

Supports + – × ÷   reciprocal, negate, compare

Untitled Verilog Effort (Isaac Yonemoto)

Julia and Verilog

8, 16, 32, ES=0

No

Unknown

Comprehensively tested for 8-bit, no known bugs

Intended for Deep Learning applications Addition, Subtraction and Multiplication only. A proof of concept matrix multiplier has been built, but is off-spec in its precision

Tokyo Tech (Artur Podobas)

FPGA

16, 32, extendable

No

“2 GHz”, not translated to Mpops/s

Partial; known rounding bugs

Yet to be open-source

Bosch

(Rohit Buddhiram Chaurasiya)

Verilog generator for VLSI, FPGA

All

No

Similar to floats of same bit size

Limited testing; no known bugs

May soon be used in commercial products to reduce bit size needed

REX Computing

(Thomas Sohmers)

FPGA version of the “Neo” VLIW processor with posit numeric unit

32

No

~1.2 Gpops/s

Extensive; no known bugs

No divide or square root. First full processor design to replace floats with posits.

Calligo Tech “Posit Numeric Unit (PNU)”

(Vijay Holimath)

FPGA; first working posit hardware

32

Claimed, not yet tested

~0.5 Mpops/s

Extensive tests, not exhaustive. No known bugs.

Single-op accelerator approach; allows direct execution of C codes written for floats. + – × tested; ÷ √ claimed

Lombiq Technologies

(Zoltán Lehóczky and team)

C# with Hastlayer for hardware generation

32 initially, adjustable with effort

Yes

Not fast

Partial

Requires Microsoft .Net APIs

IBM-TACC (Jianyu Chen)

Specific-purpose FPGA

32

Yes

16–64 Gpops/s

Only one known case tested

Does 128-by-128 matrix-matrix multiplication (SGEMM) using quire.

IIT-Madras “SHAKTI”

(V. Kamakoti, Sugandha Tiwari)

RISC-V processor with posit ALU

Unknown

Unknown

Unknown

Unknown

Difficult to engage via email

Manish Kumar Jaiswal

HDL posit generator

Unknown

No

NA

Unknown

Incorrect (truncated) rounding for now; plans to correct

 

Legend:

 

Hardware

 

Software

 

Hardware & Software