Abstract:
Arithmetic accelerators are always in demand for fast computations and logic operations. Here, posit arithmetic plays an important role; it outperforms the traditional IEEE-754 floating-point in terms of accuracy and dynamic range. This paper proposes efficient sequential architectures for posit adder/subtractor and multiplier that work as per the desired bit size of operands. Here, 32-bit architecture with different exponent size ES has been designed with a control unit. FPGA implementations of these architectures have been done on the Xilinx Virtex-7 xc7vx330t-3ffg1157 and Zynq UltraScale+ MPSoC ZCU102 device. In comparison with existing work, it is observed that the datapath delay is lowered by 64.64% for 32-bit adders and 52.66% for a 32-bit multiplier on the Virtex-7 FPGA device. In addition, the area-delay (AD) product is reduced by 52.69% and 69.30% for the 32-bit posit adder and multiplier, respectively. Also, the proposed design has reduced dynamic power than existing architectures.

[Slides]

Abstract:
The article is focused on the Sets-of-Real-Numbers (SORN) format for digital arithmetic and signal processing. The format derives from the universal numbers (unum) and has already proven to be a valuable alternative to legacy formats like fixed point or floating point. The obvious and, thus, main challenge of SORN arithmetic is degenerating accuracy due to increasing intervals widths. The authors consider three fused SORN arithmetic operations such as addition, multiplication and multiply-add and proposed an approach to reduce the interval growth as well as to improve their accuracy. The evaluation on accuracy and hardware performance show that the accuracy can be improved for up to 60% while the hardware complexity demonstrates from moderate to high increase.

[Slides]

Enjoy the break!

Abstract:
Error resilience in neural networks has allowed for the adoption of low-precision floating-point (float) representations for mixed-precision training to improve efficiency. 16-bit float representations were the first to be experimented with for this purpose. Although, the IEEE 754 standard had long defined a 16-bit float representation, several other alternatives targeting mixed-precision training have also emerged. However, their varying numerical properties and differing hardware characteristics among other things make them more or less suitable for the task. Therefore, there is no clear choice of a 16-bit floating-point representation for neural network training that is commonly accepted. In this work, we evaluate all proposed 16-bit float variants and upcoming posit number representations on a set of Convolutional Neural Networks (CNNs) and other benchmarks to compare their suitability for neural network training. Posits generally achieve better results, indicating that their non-uniform accuracy distribution is more conducive for the training task. Our analysis suggests that instead of having the same accuracy for all weight values, as is the case with floats, having more accuracy for the weights with larger magnitude and higher frequency improves the training accuracy, thereby challenging previously held assumptions while bringing new insight into the dynamic range and precision requirements. We also evaluate their efficiency on hardware for mixed-precision training based on FPGA implementations. Finally, we propose the use of the distribution of network weight values as a heuristic for selecting the number representation to be used.

[Slides]

Abstract:
Various Kalman filter mechanizations are proposed in the literature to minimize numerical instabilities due to floating point rounding and precision in computers. Theoretically all these mechanizations should lead to identical results but in practice, numerical differences arise due to floating point representation used to perform the computations. The IEEE754 floating point format is the most widely used representation in computers today, because of which we focus on the numerical issues arising in Kalman filters due to this format. These numerical issues can cause the filter to diverge (for example the positive definiteness of the covariance matrix is lost) which is undesirable, especially in a real-time, mission critical hardware. In this work, we study the applicability of Posit, which is an alternative floating point representation, with same bit length (compared to IEEE 754 floats) to improve the stability of Kalman filters. In this work we show the benefits of using Posit over IEEE floating points and support the claim with a few case studies.

[Slides]

Abstract:
Conventionally, the front-end Digital Signal Processing (DSP) for applications in radio astronomy employed low-precision fixed-point arithmetic. However, the next-generation large-scale projects for radio astronomy such as the Square Kilometre Array (SKA), Atacama Large Millimeter/sub-millimeter Array (ALMA) upgrade and the proposed next-generation Very Large Array (ngVLA) have ambitious science goals that require higher sensitivities that in turn require high-precision arithmetic implementations. Also, the increasing strength, bandwidth and number of sources of Radio Frequency Interference (RFI) exacerbate the need for high-precision arithmetic. These factors lead to higher cost and power and longer design cycles for the DSP systems in radio astronomy. Meanwhile, hardware manufacturers are offering native support for low-precision floating-point number formats such as Float16 and BFloat16 and variants of those. In addition to those, ‘Posits’, a new floating-point representation has been introduced by John Gustafson and is claiming to offer better accuracy compared to Float16 under certain conditions. With these compact data formats, it is expected that signal processing systems to consume lower power and resources. For typical radio astronomical observations, the achievable sensitivity is determined by the ability to suppress RFI and the accuracy of delay correction. In the following, these two aspects are studied for the front-end DSP modules of the SKA correlator and beamformer where the coefficients are represented with Float16, BFloat16, variants of those formats and 16-bit Posits and compared against the current fixed-point representation.

[Slides]

Abstract:
The posit numeric format is getting more and more attention in recent years. Its tapered precision makes it especially suitable in many applications including machine learning computation. However, due to its dynamic component bit-width, the cost of implementing posit arithmetic in hardware is more expensive than its floating-point counterpart. To solve this cost problem, in this paper, approximate logarithmic designs for posit multiplication, division, and square root are proposed. It is found that approximate logarithmic units are more suitable for applications that tolerate large errors, such as machine learning algorithms, but require less power consumption.

[Slides]